1. Field of the Invention
The present invention relates to an apparatus and method for mapping architectural registers to physical registers, this being a process commonly referred to as register renaming.
2. Description of the Prior Art
It is known to provide data processing systems which incorporate register renaming mechanisms. In such systems, program instructions include register specifiers identifying particular architectural registers when viewed from a programmer's model point of view. Hence, from the programmer's model point of view, there are a finite set of architectural registers which can be specified by the program instructions.
In order to facilitate higher performance operation, such as for example support for out-of-order execution (either at issue or writeback) or long pipelines, it is known to utilise register renaming techniques, whereby a larger set of physical registers are actually provided by the data processing apparatus than the set of architectural registers present within the programmer's model of that data processing apparatus. This larger set of physical registers enables hazards such as write-after-write (WAW) hazards to be avoided.
Accordingly, whilst a program instruction may specify a particular architectural register to be used, register renaming mechanisms within the data processing apparatus map this architectural register to a physical register which can be different from the physical register to which another program instruction specifying the same architectural register is mapped. Thus, the execution of the two program instructions specifying the same architectural register may be facilitated by use of different physical registers within the data processing apparatus.
The register renaming mechanism of known systems keeps track of which physical registers have been mapped to which architectural registers, and the relative ordering of the program instructions within the original program flow so that the proper behaviour and processing results are ensured. Examples of known register renaming techniques are described for example in commonly owned U.S. Pat. No. 7,624,253 and U.S. Pat. No. 7,590,826, the entire contents of which are hereby incorporated by reference.
Considering the set of physical registers, some of those registers are required to provide a mapping for all of the architectural registers, whilst the remaining registers are available to the renaming engine to use with the aim of achieving better performance. For example, if there are 30 architectural registers and 56 physical registers, then 30 physical registers are required to maintain a view of the architectural registers, leaving 26 physical registers available to ease register contention, and accordingly achieve better performance.
In some instances, it would be desirable to increase the number of physical registers available for remapping, so as to allow for further performance improvements. However, design constraints, such as frequency or power consumption, put a constraint on the size of the set of physical registers, with any increase in the size of the set of physical registers increasing the area and power consumption of the design, and potentially impacting the frequency of the design.
One known technique for seeking to free up more physical registers for use by the renaming engine involves storing a logic zero value in a particular one of the physical registers, hereafter referred to as register zero. Then, for any architectural register having a null value, instead of using a dedicated physical register from the set of physical registers, the renaming engine simply maps that architectural register to register zero. Clearly if multiple architectural registers have a null value, then they can all be mapped to register zero, thereby increasing the pool of physical registers available for mapping by the register renaming engine. Accordingly, various prior art techniques recommend zeroing registers that are unused, so that they can be mapped by the renaming engine to register zero. For example, considering the earlier example of 30 architectural registers and 56 physical registers, if all of the architectural registers have their values initialised to zero, then following initialisation, all of the architectural registers can be mapped to register zero, hence leaving 55 physical registers in the pool of available registers. Then, as each register gets written to with a value, it will be mapped to another physical register.
However, such an approach does require the operating system or application to be modified to force the software to write a logic zero value to any unused registers. Accordingly, it would be desirable to provide a technique which enabled the pool of available physical registers to be increased without increasing the overall size of the set of physical registers, and without requiring modification of the operation system or applications to force a logic zero value to be written into unused registers.